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IWSOC
2005
IEEE
151views Hardware» more  IWSOC 2005»
13 years 10 months ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
Eric Tell, Anders Nilsson, Dake Liu
ESTIMEDIA
2007
Springer
13 years 8 months ago
Still Image Processing on Coarse-Grained Reconfigurable Array Architectures
Due to the increasing demands on efficiency, performance and flexibility reconfigurable computational architectures are very promising candidates in embedded systems design. Recent...
Matthias Hartmann, Vasileios (Vassilis) Pantazis, ...
AFRICACRYPT
2009
Springer
13 years 2 months ago
Efficient Acceleration of Asymmetric Cryptography on Graphics Hardware
Graphics processing units (GPU) are increasingly being used for general purpose computing. We present implementations of large integer modular exponentiation, the core of public-ke...
Owen Harrison, John Waldron
CSC
2006
13 years 6 months ago
A Hybrid Number Representation Scheme Based on Symmetric Level-Index Arithmetic
- Symmetric level-index arithmetic was introduced to overcome the problems of overflow and underflow in scientific computations. A hybrid SLI-FLP number system, together with some ...
Xunyang Shen, Peter Turner
JPDC
2008
138views more  JPDC 2008»
13 years 4 months ago
Efficient parallel implementation of iterative reconstruction algorithms for electron tomography
Electron tomography (ET) combines electron microscopy and the principles of tomographic imaging in order to reconstruct the threedimensional structure of complex biological specim...
José-Jesús Fernández, Dan Gor...