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» Improving Pipelined Soft Processors with Multithreading
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VLDB
2005
ACM
121views Database» more  VLDB 2005»
13 years 10 months ago
Improving Database Performance on Simultaneous Multithreading Processors
Simultaneous multithreading (SMT) allows multiple threads to supply instructions to the instruction pipeline of a superscalar processor. Because threads share processor resources,...
Jingren Zhou, John Cieslewicz, Kenneth A. Ross, Mi...
PPL
2008
63views more  PPL 2008»
13 years 5 months ago
Using Hardware Multithreading to Overcome Broadcast/Reduction Latency in an Associative SIMD Processor
The latency of broadcast/reduction operations has a significant impact on the performance of SIMD processors. This is especially true for associative programs, which make extensiv...
Kevin Schaffer, Robert A. Walker
CATA
2004
13 years 6 months ago
The Instruction Execution Mechanism for Responsive Multithreaded Processor
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
Tstomu Itou, Nobuyuki Yamasaki
ISPASS
2007
IEEE
13 years 11 months ago
An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures
Semiconductor transient faults (i.e. soft errors) have become an increasingly important threat to microprocessor reliability. Simultaneous multithreaded (SMT) architectures exploi...
Wangyuan Zhang, Xin Fu, Tao Li, José A. B. ...
ICPP
2008
IEEE
13 years 11 months ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...