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» Improving Placement under the Constant Delay Model
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DATE
2003
IEEE
69views Hardware» more  DATE 2003»
13 years 10 months ago
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information
In today’s deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field prog...
Ulrich Seidl, Klaus Eckl, Frank M. Johannes
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
13 years 11 months ago
Lens aberration aware timing-driven placement
Process variations due to lens aberrations are to a large extent systematic, and can be modeled for purposes of analyses and optimizations in the design phase. Traditionally, vari...
Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qi...
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
13 years 7 months ago
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay,...
ICCAD
1998
IEEE
105views Hardware» more  ICCAD 1998»
13 years 9 months ago
Fanout optimization under a submicron transistor-level delay model
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
Pasquale Cocchini, Massoud Pedram, Gianluca Piccin...
NETWORKING
2008
13 years 6 months ago
Cache Placement Optimization in Hierarchical Networks: Analysis and Performance Evaluation
Caching popular content in the Internet has been recognized as one of the effective solution to alleviate network congestion and accelerate user information access. Sharing and coo...
Wenzhong Li, Edward Chan, Yilin Wang, Daoxu Chen, ...