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» Improving Placement under the Constant Delay Model
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FPGA
2005
ACM
80views FPGA» more  FPGA 2005»
13 years 11 months ago
Simultaneous timing-driven placement and duplication
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
Gang Chen, Jason Cong
ICCAD
2008
IEEE
223views Hardware» more  ICCAD 2008»
14 years 2 months ago
Decoupling capacitance allocation for timing with statistical noise model and timing analysis
Abstract— This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a...
Takashi Enami, Masanori Hashimoto, Takashi Sato
MASCOTS
2010
13 years 7 months ago
An Analytical Model with Improved Accuracy of IEEE 802.11 Protocol Under Unsaturated Conditions
In this work the authors present an analytical model that -- compared to previously published work -- more accurately captures the delay of IEEE 802.11 protocol under low, medium,...
Kumaran Vijayasankar, Azar Taufique, Lakshmi Naras...
BROADNETS
2007
IEEE
14 years 3 days ago
Modeling and performance analysis of an improved DCF-based mechanism under noisy channel
The ISM free-licence band is highly used by wireless technologies such IEEE 802.11, Bluetooth as well as private wireless schemes. This huge utilisation increases dramatically the ...
Adlen Ksentini, Marc Ibrahim
DATE
2002
IEEE
74views Hardware» more  DATE 2002»
13 years 10 months ago
Maze Routing with Buffer Insertion under Transition Time Constraints
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao