63 search results - page 2 / 13 » Improving Power and Data Efficiency with Threaded Memory Mod... |
ICA3PP
2007
Springer
13 years 7 months ago
2007
Springer
In this paper we present the thread migration mechanism of DSM-PEPE, a multithreaded distributed shared memory system. DSM systems like DSM-PEPE provide a parallel environment to h...
HIPC
2007
Springer
13 years 12 months ago
2007
Springer
- With the increased complexity of platforms coupled with data centers’ servers sprawl, power consumption is reaching unsustainable limits. Memory is an important target for plat...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
In programmable embedded systems, the memory subsystem represents a major cost, performance and power bottleneck. To optimize the system for such different goals, the designer wou...
ICPP
2009
IEEE
14 years 12 days ago
2009
IEEE
Parallel simulation is a technique to accelerate microarchitecture simulation of CMPs by exploiting the inherent parallelism of CMPs. In this paper, we explore the simulation para...
CLUSTER
2009
IEEE
13 years 9 months ago
2009
IEEE
Abstract--This paper proposes an analytical model to estimate the cost of running an affinity-based thread schedule on multicore systems. The model consists of three submodels to e...