24 search results - page 3 / 5 » Improving Processor Performance by Simplifying and Bypassing... |
HPCA
2006
IEEE
14 years 5 months ago
2006
IEEE
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
ESTIMEDIA
2005
Springer
13 years 11 months ago
2005
Springer
Designing Application-Specific Instruction-set Processors (ASIPs) usually requires designing a custom datapath, and modifying instruction-set, instruction decoder, and compiler. A...
CCGRID
2003
IEEE
13 years 10 months ago
2003
IEEE
I/O bottlenecks are already a problem in many largescale applications that manipulate huge datasets. This problem is expected to get worse as applications get larger, and the I/O ...
HPCA
2012
IEEE
12 years 28 days ago
2012
IEEE
The least recently used (LRU) replacement policy performs poorly in the last-level cache (LLC) because temporal locality of memory accesses is filtered by first and second level...
DEBS
2008
ACM
13 years 7 months ago
2008
ACM
In event stream applications, events flow through a network of components that perform various types of operations, e.g., filtering, aggregation, transformation. When the operatio...