10 search results - page 2 / 2 » Improving Value Communication for Thread-Level Speculation |
ISPASS
2005
IEEE
13 years 11 months ago
2005
IEEE
Communication misses--those serviced by dirty data in remote caches--are a pressing performance limiter in shared-memory multiprocessors. Recent research has indicated that tempor...
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...
JILP
2000
13 years 5 months ago
2000
Load latency remains a signi cant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Predi...
ASPLOS
2008
ACM
13 years 7 months ago
2008
ACM
Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to e...
CHI
1999
ACM
13 years 10 months ago
1999
ACM
The past decades have seen huge improvements in computer systems but these have proved difficult to translate into comparable improvements in the usability and social integration)...