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ERSA
2008
185views Hardware» more  ERSA 2008»
13 years 6 months ago
Design Framework for Partial Run-Time FPGA Reconfiguration
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...
Chris Conger, Ann Gordon-Ross, Alan D. George
DATE
2010
IEEE
183views Hardware» more  DATE 2010»
13 years 10 months ago
Monolithically stackable hybrid FPGA
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...
Dmitri Strukov, Alan Mishchenko
ERSA
2010
152views Hardware» more  ERSA 2010»
13 years 3 months ago
Persistent CAD for in-the-field Power Optimization
A major focus within the Integrated Chip (IC) industry is reducing power consumption of devices. In this paper, we explore the idea of persistent CAD algorithms that constantly imp...
Peter Jamieson
EPIA
2007
Springer
13 years 11 months ago
Improving Evolutionary Algorithms with Scouting
The goal of an Evolutionary Algorithm(EA) is to find the optimal solution to a given problem by evolving a set of initial potential solutions. When the problem is multi-modal, an ...
Konstantinos Bousmalis, Gillian M. Hayes, Jeffrey ...
BMCBI
2007
233views more  BMCBI 2007»
13 years 5 months ago
160-fold acceleration of the Smith-Waterman algorithm using a field programmable gate array (FPGA)
Background: To infer homology and subsequently gene function, the Smith-Waterman (SW) algorithm is used to find the optimal local alignment between two sequences. When searching s...
Isaac T. S. Li, Warren Shum, Kevin Truong