71 search results - page 3 / 15 » Improving memory bank-level parallelism in the presence of p... |
CCGRID
2010
IEEE
13 years 7 months ago
2010
IEEE
Although shared memory programming models show good programmability compared to message passing programming models, their implementation by page-based software distributed shared m...
HPCA
1998
IEEE
13 years 10 months ago
1998
IEEE
A key challenge in achieving high performance on software DSM systems is overcoming their relatively large communication latencies. In this paper, we consider two techniques which...
HPCA
2009
IEEE
14 years 6 months ago
2009
IEEE
Linked data structure (LDS) accesses are critical to the performance of many large scale applications. Techniques have been proposed to prefetch such accesses. Unfortunately, many...
PPSC
1997
13 years 7 months ago
1997
Sparse matrix-vector multiplication is an important kernel that often runs inefficiently on superscalar RISC processors. This paper describes techniques that increase instruction-...
HPCA
2003
IEEE
14 years 6 months ago
2003
IEEE
Although caches for decades have been the backbone of the memory system, the speed gap between CPU and main memory suggests their augmentation with prefetching mechanisms. Recentl...