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DATE
2006
IEEE
159views Hardware» more  DATE 2006»
13 years 11 months ago
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has be...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...
DAMON
2007
Springer
13 years 11 months ago
A general framework for improving query processing performance on multi-level memory hierarchies
We propose a general framework for improving the query processing performance on multi-level memory hierarchies. Our motivation is that (1) the memory hierarchy is an important pe...
Bingsheng He, Yinan Li, Qiong Luo, Dongqing Yang
ISSS
2000
IEEE
111views Hardware» more  ISSS 2000»
13 years 9 months ago
Systematic Data Reuse Exploration Methodology for Irregular Access Patterns
Efficient use of an optimized custom memory hierarchy to exploit temporal locality in the memory accesses on array signals can have a very large impact on the power consumption i...
Tanja Van Achteren, Rudy Lauwereins, Francky Catth...
IPPS
1997
IEEE
13 years 9 months ago
View Caching: Efficient Software Shared Memory for Dynamic Computations
Software distributed shared memory (DSM) techniques, while effective on applications with coarse-grained sharing, yield poor performance for the fine-grained sharing encountered i...
Vijay Karamcheti, Andrew A. Chien
PCI
2005
Springer
13 years 11 months ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...