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HIPEAC
2011
Springer
12 years 4 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
ISCA
2006
IEEE
182views Hardware» more  ISCA 2006»
13 years 11 months ago
Cooperative Caching for Chip Multiprocessors
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...
Jichuan Chang, Gurindar S. Sohi
TJS
1998
101views more  TJS 1998»
13 years 4 months ago
Compiler Support for Array Distribution on NUMA Shared Memory Multiprocessors
Management of program data to improve data locality and reduce false sharing is critical for scaling performanceon NUMA shared memorymultiprocessors. We use HPF-like data decomposi...
Tarek S. Abdelrahman, Thomas N. Wong
DATE
2008
IEEE
171views Hardware» more  DATE 2008»
13 years 11 months ago
Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
Arno Moonen, Marco Bekooij, Rene van den Berg, Jef...
DATE
2004
IEEE
173views Hardware» more  DATE 2004»
13 years 8 months ago
Supporting Cache Coherence in Heterogeneous Multiprocessor Systems
In embedded system-on-a-chip (SoC) applications, the need for integrating heterogeneous processors in a single chip is increasing. An important issue in integrating heterogeneous ...
Taeweon Suh, Douglas M. Blough, Hsien-Hsin S. Lee