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TSE
1998
102views more  TSE 1998»
13 years 4 months ago
Designing Masking Fault-Tolerance via Nonmasking Fault-Tolerance
—Masking fault-tolerance guarantees that programs continually satisfy their specification in the presence of faults. By way of contrast, nonmasking fault-tolerance does not guara...
Anish Arora, Sandeep S. Kulkarni
CF
2004
ACM
13 years 10 months ago
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable a...
Fernanda Lima Kastensmidt, Gustavo Neuberger, Luig...
AICCSA
2006
IEEE
137views Hardware» more  AICCSA 2006»
13 years 11 months ago
Modeling Redundancy: Quantitative and Qualitative Models
Redundancy is a system property that generally refers to duplication of state information or system function. While redundancy is usually investigated in the context of fault tole...
Ali Mili, Lan Wu, Frederick T. Sheldon, Mark Shere...
DFT
2009
IEEE
189views VLSI» more  DFT 2009»
13 years 12 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
DSN
2007
IEEE
13 years 11 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...