24 search results - page 1 / 5 » Improving the Throughput of a Pipeline by Insertion of Delay... |
ISCA
1998
IEEE
13 years 9 months ago
1998
IEEE
HPCA
2000
IEEE
13 years 9 months ago
2000
IEEE
Efficiency of synchronization mechanisms can limit the parallel performance of many shared-memory applications. In addition, the ever increasing performance gap between processor...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper, we study the full-chp interconnect power modeling. ,We show that repeater,insertion is no longer sufficient to achievethe targetfrequencies specifiedhy ITRS, and de...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
ASYNC
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper introduces several new asynchronous pipeline designs which offer high throughput as well as low latency. The designs target dynamic datapaths, both dualrail as well as ...