Sciweavers

12 search results - page 2 / 3
» Improving the parallelism of iterative methods by aggressive...
Sort
View
MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
13 years 5 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....
ICPPW
2008
IEEE
13 years 11 months ago
Performance Analysis and Optimization of Parallel Scientific Applications on CMP Cluster Systems
Chip multiprocessors (CMP) are widely used for high performance computing. Further, these CMPs are being configured in a hierarchical manner to compose a node in a cluster system....
Xingfu Wu, Valerie E. Taylor, Charles W. Lively, S...
PDP
2008
IEEE
13 years 11 months ago
Just-In-Time Scheduling for Loop-based Speculative Parallelization
Scheduling for speculative parallelization is a problem that remained unsolved despite its importance. Simple methods such as Fixed-Size Chunking (FSC) need several ‘dry-runs’...
Diego R. Llanos Ferraris, David Orden, Belé...
IPPS
1999
IEEE
13 years 9 months ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
IPPS
1998
IEEE
13 years 9 months ago
Register-Sensitive Software Pipelining
In this paper, we propose an integrated approach for register-sensitive software pipelining. In this approach, the heuristics proposed in the stage scheduling method of Eichenberg...
Amod K. Dani, V. Janaki Ramanan, Ramaswamy Govinda...