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MICRO
2007
IEEE
168views Hardware» more  MICRO 2007»
14 years 17 days ago
Global Multi-Threaded Instruction Scheduling
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
Guilherme Ottoni, David I. August
ASPLOS
2008
ACM
13 years 8 months ago
Parallelizing security checks on commodity hardware
Speck1 is a system that accelerates powerful security checks on commodity hardware by executing them in parallel on multiple cores. Speck provides an infrastructure that allows se...
Edmund B. Nightingale, Daniel Peek, Peter M. Chen,...
HPCA
2008
IEEE
14 years 6 months ago
System level analysis of fast, per-core DVFS using on-chip switching regulators
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...
Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, Dav...
ISCA
2008
IEEE
137views Hardware» more  ISCA 2008»
14 years 21 days ago
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...
Engin Ipek, Onur Mutlu, José F. Martí...
ICS
2010
Tsinghua U.
13 years 4 months ago
An approach to resource-aware co-scheduling for CMPs
We develop real-time scheduling techniques for improving performance and energy for multiprogrammed workloads that scale nonuniformly with increasing thread counts. Multithreaded ...
Major Bhadauria, Sally A. McKee