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» Improving yield and reliability of chip multiprocessors
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HIPEAC
2010
Springer
14 years 2 months ago
Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors
As CMOS feature sizes venture deep into the nanometer regime, wearout mechanisms including negative-bias temperature instability and timedependent dielectric breakdown can severely...
Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott ...
EDCC
2008
Springer
13 years 6 months ago
A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...
Roman Obermaisser, Hubert Kraut, Christian El Sall...
ASPDAC
2008
ACM
174views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty
In modern circuit design, it is difficult to provide reliable parametric yield prediction since the real distribution of process data is hard to measure. Most existing approaches ...
Jin Sun, Yue Huang, Jun Li, Janet Meiling Wang
ISQED
2009
IEEE
136views Hardware» more  ISQED 2009»
13 years 11 months ago
NBTI aware workload balancing in multi-core systems
—As device feature size continues to shrink, reliability becomes a severe issue due to process variation, particle-induced transient errors, and transistor wear-out/stress such a...
Jin Sun, Avinash Karanth Kodi, Ahmed Louri, Janet ...
MICRO
2006
IEEE
104views Hardware» more  MICRO 2006»
13 years 11 months ago
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Although silicon optical technology is still in its formative stages, and the more near-term application is chip-to-chip communication, rapid advances have been made in the develo...
Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, Jo...