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ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
13 years 9 months ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
CF
2007
ACM
13 years 8 months ago
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors
Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward d...
Juan M. Cebrian, Juan L. Aragón, José...
PACS
2004
Springer
141views Hardware» more  PACS 2004»
13 years 10 months ago
Energy-Aware Data Prefetching for General-Purpose Programs
There has been intensive research on data prefetching focusing on performance improvement, however, the energy aspect of prefetching is relatively unknown. Our experiments show th...
Yao Guo, Saurabh Chheda, Israel Koren, C. Mani Kri...
TC
2008
13 years 4 months ago
Counter-Based Cache Replacement and Bypassing Algorithms
Recent studies have shown that, in highly associative caches, the performance gap between the Least Recently Used (LRU) and the theoretical optimal replacement algorithms is large,...
Mazen Kharbutli, Yan Solihin
IPPS
2007
IEEE
13 years 11 months ago
Leakage Energy Reduction in Value Predictors through Static Decay
As process technology advances toward deep submicron (below 90nm), static power becomes a new challenge to address for energy-efficient high performance processors, especially for...
Juan M. Cebrian, Juan L. Aragón, José...