15 search results - page 1 / 3 » Input Ordering in Concurrent Checkers to Reduce Power Consum... |
DFT
2002
IEEE
13 years 10 months ago
2002
IEEE
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
PPOPP
2005
ACM
13 years 10 months ago
2005
ACM
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...
ICS
2005
Tsinghua U.
13 years 10 months ago
2005
Tsinghua U.
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
This paper presents a new methodology for system-level power and performance analysis of wireless multimedia systems. More precisely, we introduce an analytical approach based on ...