78 search results - page 14 / 16 » Instruction Cache Fetch Policies for Speculative Execution |
MICRO
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
MICRO
2000
IEEE
13 years 10 months ago
2000
IEEE
Modern microprocessors employ increasingly complicated branch predictors to achieve instruction fetch bandwidth that is sufficient for wide out-of-order execution cores. While ex...
LCTRTS
2007
Springer
13 years 12 months ago
2007
Springer
As mobile phones become increasingly multifunctional, the number and size of applications installed in phones are rapidly increasing. Consequently, mobile phones require more hard...
HPCC
2007
Springer
13 years 12 months ago
2007
Springer
Simultaneous Multithreading (SMT)[1][2] and chip multiprocessors (CMP) processors [3] have emerged as the mainstream computing platform in major market segments, including PC, serv...
IEEEPACT
2009
IEEE
13 years 3 months ago
2009
IEEE
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...