78 search results - page 4 / 16 » Instruction Cache Fetch Policies for Speculative Execution |
EUROMICRO
1998
IEEE
13 years 10 months ago
1998
IEEE
In this paper we present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dep...
IEEEPACT
1999
IEEE
13 years 10 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...
ISHPC
2003
Springer
13 years 11 months ago
2003
Springer
Abstract. In SMT processors several threads run simultaneously to increase available ILP, sharing but competing for resources. The instruction fetch policy plays a key role, determ...
EUROPAR
2005
Springer
13 years 11 months ago
2005
Springer
Instruction delivery is a critical component for wide-issue processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and ba...
HPCA
2007
IEEE
14 years 6 months ago
2007
IEEE
A thread executing on a simultaneous multithreading (SMT) processor that experiences a long-latency load will eventually stall while holding execution resources. Existing long-lat...