138 search results - page 3 / 28 » Instruction Scheduling and Executable Editing |
ML
2002
ACM
13 years 4 months ago
2002
ACM
The execution order of a block of computer instructions on a pipelined machine can make a difference in running time by a factor of two or more. Compilers use heuristic schedulers...
TSP
2008
13 years 4 months ago
2008
The focus of this paper is on VLIW instruction scheduling that minimizes the variation of power consumed by the processor during the execution of a target program. We use rough set...
MICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
A machine’s performance is the product of its IPC (Instructions Per Cycle) and clock frequency. Recently, Palacharla, Jouppi, and Smith [3] warned that the dynamic instruction s...
IJPP
2000
13 years 4 months ago
2000
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
RSP
2000
IEEE
13 years 9 months ago
2000
IEEE
Reconfigurable instruction set processors have the capability to adapt their instruction sets to the application being executed through a reconfiguration in their hardware. Throug...