106 search results - page 2 / 22 » Instruction Set Design and Optimizations for Address Computa... |
RTCSA
2006
IEEE
13 years 11 months ago
2006
IEEE
To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constr...
DAC
1995
ACM
13 years 9 months ago
1995
ACM
—We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventiona...
DCC
2007
IEEE
14 years 5 months ago
2007
IEEE
Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software de...
ICASSP
2008
IEEE
13 years 12 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
LCTRTS
2007
Springer
13 years 11 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...