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» Instruction level power model of microcontrollers
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ISPASS
2009
IEEE
14 years 2 days ago
Analyzing CUDA workloads using a detailed GPU simulator
Modern Graphic Processing Units (GPUs) provide sufficiently flexible programming models that understanding their performance can provide insight in designing tomorrow’s manyco...
Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, He...
PLDI
2005
ACM
13 years 10 months ago
Pin: building customized program analysis tools with dynamic instrumentation
Robust and powerful software instrumentation tools are essential for program analysis tasks such as profiling, performance evaluation, and bug detection. To meet this need, we ha...
Chi-Keung Luk, Robert S. Cohn, Robert Muth, Harish...
MICRO
2008
IEEE
208views Hardware» more  MICRO 2008»
13 years 11 months ago
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
Wangyuan Zhang, Tao Li
JUCS
2000
120views more  JUCS 2000»
13 years 5 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi