7 search results - page 2 / 2 » Instruction scheduling for a tiled dataflow architecture |
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
CGO
2005
IEEE
13 years 10 months ago
2005
IEEE
The growing complexity of modern processors has made the generation of highly efficient code increasingly difficult. Manual code generation is very time consuming, but it is oft...