24 search results - page 3 / 5 » Integrating superscalar processor components to implement re... |
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
Transient errors are one of the major reasons for system downtime in many systems. While prior research has mainly focused on the impact of transient errors on datapath, caches an...
NOCS
2007
IEEE
14 years 1 days ago
2007
IEEE
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
ISLPED
2003
ACM
13 years 11 months ago
2003
ACM
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
MICRO
2008
IEEE
14 years 4 days ago
2008
IEEE
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
HPCA
1998
IEEE
13 years 10 months ago
1998
IEEE
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...