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» Integration of VHDL into a system design environment
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RSP
2005
IEEE
162views Control Systems» more  RSP 2005»
13 years 11 months ago
SyCE: An Integrated Environment for System Design in SystemC
We present an integrated system design environment for SystemC, called SyCE. The system consists of several components for efficient analysis, verification and debugging of Syst...
Rolf Drechsler, Görschwin Fey, Christian Genz...
IPPS
2007
IEEE
14 years 7 days ago
Integrated Environment for Embedded Control Systems Design
The motivation of our work is to make a design tool for distributed embedded systems compliant with HIS and AUTOSAR. The tool is based on Processor Expert, a component oriented de...
Roman Bartosinski, Zdenek Hanzálek, Petr St...
DATE
1997
IEEE
95views Hardware» more  DATE 1997»
13 years 10 months ago
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications
A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modem design from the link level to t...
Patrick Schaumont, Serge Vernalde, Luc Rijnders, M...
VLSID
2004
IEEE
292views VLSI» more  VLSID 2004»
14 years 6 months ago
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
Jeremy Chan, Sri Parameswaran
LCPC
2001
Springer
13 years 10 months ago
Bridging the Gap between Compilation and Synthesis in the DEFACTO System
Abstract. The DEFACTO project - a Design Environment For Adaptive Computing TechnOlogy - is a system that maps computations, expressed in high-level languages such as C, directly o...
Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoun...