Sciweavers

9 search results - page 1 / 2
» Intel's New AES Instructions for Enhanced Performance and Se...
Sort
View
FSE
2009
Springer
159views Cryptology» more  FSE 2009»
13 years 11 months ago
Intel's New AES Instructions for Enhanced Performance and Security
The Advanced Encryption Standard (AES) is the Federal Information Processing Standard for symmetric encryption. It is widely believed to be secure and efficient, and is therefore b...
Shay Gueron
CHES
2007
Springer
327views Cryptology» more  CHES 2007»
13 years 11 months ago
On the Power of Bitslice Implementation on Intel Core2 Processor
Abstract. This paper discusses the state-of-the-art fast software implementation of block ciphers on Intel’s new microprocessor Core2, particularly concentrating on “bitslice i...
Mitsuru Matsui, Junko Nakajima
FSE
2006
Springer
117views Cryptology» more  FSE 2006»
13 years 8 months ago
How Far Can We Go on the x64 Processors?
This paper studies the state-of-the-art software optimization methodology for symmetric cryptographic primitives on the new 64-bit x64 processors, AMD Athlon64 (AMD64) and Intel Pe...
Mitsuru Matsui
ICCD
2000
IEEE
106views Hardware» more  ICCD 2000»
13 years 9 months ago
Fast Subword Permutation Instructions Using Omega and Flip Network Stages
This paper proposes a new way of efficiently doing arbitrary ¢ -bit permutations in programmable processors modeled on the theory of omega and flip networks. The new omflip ins...
Xiao Yang, Ruby B. Lee
IH
2005
Springer
13 years 10 months ago
Data Hiding in Compiled Program Binaries for Enhancing Computer System Performance
Abstract. Information hiding has been studied in many security applications such as authentication, copyright management and digital forensics. In this work, we introduce a new app...
Ashwin Swaminathan, Yinian Mao, Min Wu, Krishnan K...