12 search results - page 3 / 3 » Interconnect delay minimization through interlayer via place... |
GLVLSI
2009
IEEE
14 years 3 days ago
2009
IEEE
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
ICCAD
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...