34 search results - page 2 / 7 » Interconnect power and delay optimization by dynamic program... |
SLIP
2009
ACM
13 years 11 months ago
2009
ACM
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
CN
2007
13 years 4 months ago
2007
— Energy efficient operation is of paramount importance for battery-powered wireless nodes. In an effort to conserve energy, standard protocols for WLANs have the provision for w...
NN
2008
Springer
13 years 4 months ago
2008
Springer
Wide-area coordinating control is becoming an important issue and a challenging problem in the power industry. This paper proposes a novel optimal wide-area coordinating neurocont...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...