7 search results - page 1 / 2 » Interconnections in Multi-Core Architectures: Understanding ... |
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
HPCA
2007
IEEE
14 years 5 months ago
2007
IEEE
Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an ...
CASES
2007
ACM
13 years 9 months ago
2007
ACM
Micro-Electro-Mechanical Systems (MEMS) combine lithographically formed mechanical structures with electrical elements to create physical systems that operate on the scale of micr...
CDES
2008
13 years 6 months ago
2008
Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory ove...
DAC
2011
ACM
12 years 5 months ago
2011
ACM
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...