30 search results - page 2 / 6 » Interfacing Reconfigurable Logic with a CPU |
FPL
2007
Springer
13 years 12 months ago
2007
Springer
Programmable logic cores (PLCs) offer a means of providing post-fabrication re-configurability to a SoC design. Circuits implemented in a PLC will inevitably have lower timing per...
ARC
2009
Springer
13 years 10 months ago
2009
Springer
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...
RTSS
2008
IEEE
14 years 3 days ago
2008
IEEE
This paper presents algorithms that (1) facilitate systemindependent synthesis of timing-interfaces for subsystems and (2) system-level selection of interfaces to minimize CPU loa...
FPGA
2004
ACM
13 years 9 months ago
2004
ACM
Embedded systems combine a processor with dedicated logic to meet design specifications at a reasonable cost. The attempt to amalgamate two distinct design environments introduces...