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» Investigating Cache Parameters of x86 Family Processors
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SIPEW
2009
Springer
127views Hardware» more  SIPEW 2009»
13 years 9 months ago
Investigating Cache Parameters of x86 Family Processors
Abstract. The excellent performance of the contemporary x86 processors is partially due to the complexity of their memory architecture, which therefore plays a role in performance ...
Vlastimil Babka, Petr Tuma
ISPASS
2007
IEEE
13 years 11 months ago
PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 proces...
Matt T. Yourst
MICRO
1995
IEEE
97views Hardware» more  MICRO 1995»
13 years 8 months ago
Improving CISC instruction decoding performance using a fill unit
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
Mark Smotherman, Manoj Franklin
CASES
2007
ACM
13 years 8 months ago
An integrated ARM and multi-core DSP simulator
In this paper we describe the design and implementation of a flexible, and extensible, just-in-time ARM simulator designed to run co-operatively with a multi-core DSP simulator on...
Sharad Singhai, MingYung Ko, Sanjay Jinturkar, May...
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
13 years 8 months ago
Instruction Cache Fetch Policies for Speculative Execution
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grun...