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CGO
2004
IEEE
13 years 10 months ago
Custom Data Layout for Memory Parallelism
In this paper, we describe a generalized approach to deriving a custom data layout in multiple memory banks for array-based computations, to facilitate high-bandwidth parallel mem...
Byoungro So, Mary W. Hall, Heidi E. Ziegler
MINENET
2006
ACM
14 years 6 days ago
SVM learning of IP address structure for latency prediction
We examine the ability to exploit the hierarchical structure of Internet addresses in order to endow network agents with predictive capabilities. Specifically, we consider Suppor...
Robert Beverly, Karen R. Sollins, Arthur Berger
HPDC
1997
IEEE
13 years 10 months ago
Supporting Parallel Applications on Clusters of Workstations: The Intelligent Network Interface Approach
This paper presents a novel networking architecture designed for communication intensive parallel applications running on clusters of workstations (COWs) connected by highspeed ne...
Marcel-Catalin Rosu, Karsten Schwan, Richard Fujim...
IPPS
2010
IEEE
13 years 4 months ago
Structuring the execution of OpenMP applications for multicore architectures
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
François Broquedis, Olivier Aumage, Brice G...
BMCBI
2004
153views more  BMCBI 2004»
13 years 6 months ago
Computational protein biomarker prediction: a case study for prostate cancer
Background: Recent technological advances in mass spectrometry pose challenges in computational mathematics and statistics to process the mass spectral data into predictive models...
Michael Wagner, Dayanand N. Naik, Alex Pothen, Sri...