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CGO
2004
IEEE

Custom Data Layout for Memory Parallelism

8 years 7 months ago
Custom Data Layout for Memory Parallelism
In this paper, we describe a generalized approach to deriving a custom data layout in multiple memory banks for array-based computations, to facilitate high-bandwidth parallel memory accesses in modern architectures where multiple memory banks can simultaneously feed one or more functional units. We do not use a fixed data layout, but rather select application-specific layouts according to access patterns in the code. A unique feature of this approach is its flexibility in the presence of code reordering transformations, such as the loop nest transformations commonly applied to array-based computations. We have implemented this algorithm in the DEFACTO system, a design environment for automatically mapping C programs to hardware implementations for FPGA-based systems. We present experimental results for five multimedia kernels that demonstrate the benefits of this approach. Our results show that custom data layout yields results as good as, or better than, naive or fixed cyclic layout...
Byoungro So, Mary W. Hall, Heidi E. Ziegler
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where CGO
Authors Byoungro So, Mary W. Hall, Heidi E. Ziegler
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