14 search results - page 3 / 3 » L1 Data Cache Power Reduction Using a Forwarding Predictor |
HPCA
2005
IEEE
14 years 5 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...
EUROSYS
2007
ACM
14 years 2 months ago
2007
ACM
The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end...
CGO
2005
IEEE
13 years 11 months ago
2005
IEEE
To minimize the surging power consumption of microprocessors, adaptive computing environments (ACEs) where microarchitectural resources can be dynamically tuned to match a program...