Sciweavers

33 search results - page 3 / 7
» LLVA: A Low-level Virtual Instruction Set Architecture
Sort
View
DATE
2003
IEEE
86views Hardware» more  DATE 2003»
13 years 11 months ago
Layered, Multi-Threaded, High-Level Performance Design
A primary goal of high-level modeling is to efficiently explore a broad design space, converging on an optimal or near-optimal system architecture before moving to a more detaile...
Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas
IFL
2004
Springer
13 years 11 months ago
A Virtual Machine for Functional Logic Computations
Abstract. We describe the architecture of a virtual machine for executing functional logic programming languages. A distinguishing feature of our machine is that it preserves the o...
Sergio Antoy, Michael Hanus, Jimeng Liu, Andrew P....
CGO
2003
IEEE
13 years 11 months ago
Dynamic Binary Translation for Accumulator-Oriented Architectures
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
Ho-Seop Kim, James E. Smith
ISCA
2008
IEEE
205views Hardware» more  ISCA 2008»
14 years 6 days ago
VEAL: Virtualized Execution Accelerator for Loops
Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunc...
Nathan Clark, Amir Hormati, Scott A. Mahlke
CGO
2006
IEEE
13 years 12 months ago
Constructing Virtual Architectures on a Tiled Processor
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
David Wentzlaff, Anant Agarwal