52 search results - page 1 / 11 » Layout Volumes of the Hypercube |
ICPP
2000
IEEE
13 years 9 months ago
2000
IEEE
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-l...
GD
2004
Springer
13 years 10 months ago
2004
Springer
We study 3-dimensional layouts of the hypercube in a 1-active layer and general model. The problem can be understood as a graph drawing problem in 3D space and was addressed at Gr...
GD
2003
Springer
13 years 10 months ago
2003
Springer
IPPS
1999
IEEE
13 years 9 months ago
1999
IEEE
We propose the recursive grid layout scheme for deriving efficient layouts of a variety of hierarchical networks and computing upper bounds on the VLSI area of general hierarchica...
CGF
2006
13 years 4 months ago
2006
We present a novel algorithm to compute cache-efficient layouts of bounding volume hierarchies (BVHs) of polygonal models. Our approach does not make any assumptions about the cac...