4 search results - page 1 / 1 » Layout to Logic Defect Analysis for Hierarchical Test Genera... |
DDECS
2007
IEEE
13 years 11 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
MTDT
2003
IEEE
13 years 10 months ago
2003
IEEE
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
— There is a growing interest in developing low cost, low power, highly integrated biosensor systems to characterize individual cells for applications such as cell analysis, drug...
AAAI
1998
13 years 6 months ago
1998
This paper discusses the design and implementation of ESSPL, an expert system which generates security plans for alarm systems (Figure 1). Security planning is the task of determi...