18 search results - page 4 / 4 » Layout-Driven RTL Binding Techniques for High-Level Synthesi... |
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
CCL
1994
Springer
13 years 9 months ago
1994
Springer
Abstract: This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with ef...
FPL
2004
Springer
13 years 10 months ago
2004
Springer
A previous study [1] demonstrates the advantages of replacing registers by FPGA embedded memories during the storage allocation phase of High-Level Synthesis. The trend in new FPGA...