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» Leakage Energy Management in Cache Hierarchies
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IEEEPACT
2002
IEEE
13 years 9 months ago
Leakage Energy Management in Cache Hierarchies
Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan V...
ICCD
2008
IEEE
118views Hardware» more  ICCD 2008»
14 years 1 months ago
Adaptive techniques for leakage power management in L2 cache peripheral circuits
— Recent studies indicate that a considerable amount of an L2 cache leakage power is dissipated in its peripheral circuits, e.g., decoders, word-lines and I/O drivers. In additio...
Houman Homayoun, Alexander V. Veidenbaum, Jean-Luc...
ISLPED
2006
ACM
119views Hardware» more  ISLPED 2006»
13 years 10 months ago
Process variation aware cache leakage management
In a few technology generations, limitations of fabrication processes will make accurate design time power estimates a daunting challenge. Static leakage current which comprises a...
Ke Meng, Russ Joseph
ICCD
2007
IEEE
100views Hardware» more  ICCD 2007»
14 years 1 months ago
VOSCH: Voltage scaled cache hierarchies
The cache hierarchy of state-of-the-art—especially multicore—microprocessors consumes a significant amount of area and energy. A significant amount of research has been devo...
Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li
MICRO
2000
IEEE
121views Hardware» more  MICRO 2000»
13 years 8 months ago
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
Rajeev Balasubramonian, David H. Albonesi, Alper B...