62 search results - page 13 / 13 » Leakage Minimization Technique for Nanoscale CMOS VLSI |
VLSID
2005
IEEE
14 years 6 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
ISCAS
2007
IEEE
14 years 1 days ago
2007
IEEE
Abstract— We study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above wh...