39 search results - page 3 / 8 » Leakage-Aware Interconnect for On-Chip Network |
DATE
2000
IEEE
13 years 10 months ago
2000
IEEE
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
TC
2008
13 years 6 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
SBACPAD
2007
IEEE
14 years 13 days ago
2007
IEEE
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
ICCD
2006
IEEE
14 years 3 months ago
2006
IEEE
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
VLSID
2006
IEEE
14 years 6 months ago
2006
IEEE
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...