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VLSID
2007
IEEE
142views VLSI» more  VLSID 2007»
14 years 5 months ago
Controllability-driven Power Virus Generation for Digital Circuits
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekanan...
ISLPED
1996
ACM
89views Hardware» more  ISLPED 1996»
13 years 9 months ago
A novel methodology for transistor-level power estimation
Transistlw-level power simulators, which are more accurate than logic-level power estimators, have been popularly used to estimate the power dissipation of CMOS circuits. In thisp...
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, ...
TCAD
1998
127views more  TCAD 1998»
13 years 5 months ago
Gate-level power estimation using tagged probabilistic simulation
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram
ICCAD
1996
IEEE
151views Hardware» more  ICCAD 1996»
13 years 9 months ago
Expected current distributions for CMOS circuits
The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper...
Dennis J. Ciplickas, Ronald A. Rohrer
ISCAS
2007
IEEE
112views Hardware» more  ISCAS 2007»
13 years 11 months ago
A New Statistical Approach for Glitch Estimation in Combinational Circuits
— Low-power consumption has become a highly important concern for synchronous standard-cell design, and consequently mandates the use of low-power design methodologies and techni...
Ahmed Sayed, Hussain Al-Asaad