10 search results - page 2 / 2 » Limiting the number of dirty cache lines |
ICCD
2008
IEEE
14 years 1 months ago
2008
IEEE
—In this paper we examine techniques for increasing the effective bandwidth of the microprocessor offchip interconnect. We focus on mechanisms that are orthogonal to other techni...
IPPS
2005
IEEE
13 years 10 months ago
2005
IEEE
As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...
SC
1992
ACM
13 years 9 months ago
1992
ACM
We are currently developing Willow, a shared-memory multiprocessor whose design provides system capacity and performance capable of supporting over a thousand commercial microproc...
ACISICIS
2005
IEEE
13 years 10 months ago
2005
IEEE
Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle....
SIGMOD
2002
ACM
14 years 5 months ago
2002
ACM
Peer-to-Peer (P2P) systems are becoming increasingly popular as they enable users to exchange digital information by participating in complex networks. Such systems are inexpensiv...