59 search results - page 1 / 12 » Load Miss Prediction - Exploiting Power Performance Trade-of... |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
As the performance gap between processors and memory systems increases, the CPU spends more time stalled waiting for data from main memory. Critical long latency instructions, suc...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in ...
MICRO
1998
IEEE
13 years 9 months ago
1998
IEEE
Load latency remains a significant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Pred...
JILP
2000
13 years 4 months ago
2000
Load latency remains a signi cant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Predi...