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ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
13 years 9 months ago
TAPHS: thermal-aware unified physical-level and high-level synthesis
Thermal effects are becoming increasingly important during integrated circuit design. Thermal characteristics influence reliability, power consumption, cooling costs, and performan...
Zhenyu (Peter) Gu, Yonghong Yang, Jia Wang, Robert...
CSREAESA
2003
13 years 6 months ago
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
Kugan Vivekanandarajah, Thambipillai Srikanthan, C...
HPCA
2005
IEEE
14 years 5 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
13 years 10 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
CSREAESA
2003
13 years 6 months ago
A Comparative Study of Dynamic Voltage Scaling Techniques for Low-Power Video Decoding
This paper presents a comparison of power-aware video decoding techniques that utilize Dynamic Voltage Scaling (DVS) capability. Three techniques were simulated and compared in te...
Eriko Nurvitadhi, Ben Lee, Chansu Yu, Myungchul Ki...