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» Logic as Energy: A SAT-Based Approach
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ISLPED
2000
ACM
99views Hardware» more  ISLPED 2000»
13 years 9 months ago
Practical considerations of clock-powered logic
Recovering and reusing circuit energies that would otherwise be dissipated as heat can reduce the power dissipated by a VLSI chip. To accomplish this requires a power source that ...
William C. Athas
CPAIOR
2006
Springer
13 years 9 months ago
Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs
Abstract. In this paper we introduce a complex allocation and scheduling problem for variable voltage Multi-Processor System-on-Chip (MPSoC) platforms. We propose a methodology to ...
Luca Benini, Davide Bertozzi, Alessio Guerri, Mich...
IJCSS
2007
133views more  IJCSS 2007»
13 years 5 months ago
Synthesis of Read-Once Digital Hardware with Reduced Energy Delay Product
This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the...
P. Balasubramanian, S. Theja
WICOMM
2008
122views more  WICOMM 2008»
13 years 5 months ago
Energy and connectivity performance of routing groups in multi-radio multi-hop networks
This paper explores the logical device aggregation of terminals in future generation networks, where the availability of several different radio access techniques is integrated by...
Michele Rossi, Leonardo Badia, Paolo Giacon, Miche...
MICRO
2010
IEEE
173views Hardware» more  MICRO 2010»
13 years 3 months ago
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken ...