22 search results - page 2 / 5 » Logic decomposition during technology mapping |
ISQED
2005
IEEE
13 years 11 months ago
2005
IEEE
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Libraryaware constructive decomposition offers a solution to th...
FPGA
2008
ACM
13 years 6 months ago
2008
ACM
This paper presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the ite...
DAC
1998
ACM
13 years 9 months ago
1998
ACM
Recently, functional decomposition has been adopted for LUT based FPGA technology mapping with good results. In this paper, we propose a novel method for functional multipleoutput...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
— This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT ...