22 search results - page 3 / 5 » Logic decomposition during technology mapping |
FPGA
2007
ACM
13 years 12 months ago
2007
ACM
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Most FPGA technology mapping approaches either target Lookup Tables (LUTs) or relatively simple Programmable Logic Blocks (PLBs). Considering networks of PLBs during technology map...
ICCD
1996
IEEE
13 years 10 months ago
1996
IEEE
The Multi-Level Decomposition Diagrams (MLDDs) of this paper are a canonical representation of Boolean functions expliciting disjoint-support decompositions. MLDDs allow the reduc...
DOLAP
2006
ACM
13 years 11 months ago
2006
ACM
One of the most important tasks performed in the early stages of a data warehouse project is the analysis of the structure and content of the existing data sources and their inten...
ICCAD
1995
IEEE
13 years 9 months ago
1995
IEEE
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...