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JSA
2000
103views more  JSA 2000»
13 years 5 months ago
Testing and built-in self-test - A survey
As the density of VLSI circuits increases it becomes attractive to integrate dedicated test logic on a chip. This Built-in Self-Test (BIST) approach not only offers economic benef...
Andreas Steininger
3DIC
2009
IEEE
258views Hardware» more  3DIC 2009»
14 years 6 days ago
A capacitive coupling interface with high sensitivity for wireless wafer testing
—A high-sensitivity capacitive-coupling interface is presented for wireless wafer testing systems. The transmitter is a buffer that drives the transmitter pad, and the receiver c...
Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai
ITC
2003
IEEE
123views Hardware» more  ITC 2003»
13 years 10 months ago
A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic
In this paper we introduce a tool which is capable of verifying an 1149.1 test logic implementation and its compliance to the IEEE 1149.1 Standard [1][2] while providing a precise...
Kevin Melocco, Hina Arora, Paul Setlak, Gary Kunse...
TABLEAUX
2000
Springer
13 years 9 months ago
Consistency Testing: The RACE Experience
Abstract. This paper presents the results of applying RACE, a description logic system for ALCNHR+ , to modal logic SAT problems. Some aspects of the RACE architecture are discusse...
Volker Haarslev, Ralf Möller
ICST
2009
IEEE
14 years 1 days ago
Transforming and Selecting Functional Test Cases for Security Policy Testing
In this paper, we consider typical applications in which the business logic is separated from the access control logic, implemented in an independent component, called the Policy ...
Tejeddine Mouelhi, Yves Le Traon, Benoit Baudry