As the density of VLSI circuits increases it becomes attractive to integrate dedicated test logic on a chip. This Built-in Self-Test (BIST) approach not only offers economic benef...
—A high-sensitivity capacitive-coupling interface is presented for wireless wafer testing systems. The transmitter is a buffer that drives the transmitter pad, and the receiver c...
In this paper we introduce a tool which is capable of verifying an 1149.1 test logic implementation and its compliance to the IEEE 1149.1 Standard [1][2] while providing a precise...
Kevin Melocco, Hina Arora, Paul Setlak, Gary Kunse...
Abstract. This paper presents the results of applying RACE, a description logic system for ALCNHR+ , to modal logic SAT problems. Some aspects of the RACE architecture are discusse...
In this paper, we consider typical applications in which the business logic is separated from the access control logic, implemented in an independent component, called the Policy ...